Conference Agenda

Abstract:
The increasing demand for compact, efficient, and reliable power supply modules in avionic cabin systems requires advanced packaging and interconnection technologies beyond conventional PCB assembly. This work investigates the miniaturization of low-power DC-DC converters based on PCB embedding technology, with a focus on 28 V DC onboard power systems under aerospace-specific constraints.
Based on a comprehensive market, literature, and topology analysis, various converter concepts were evaluated with respect to electrical performance, component height, and suitability for PCB embedding. Buck and SEPIC topologies were identified as particularly suitable for realizing power levels of up to 5 W within strictly limited installation space. To validate the theoretical investigations, test circuits were designed, fabricated, and electrically characterized, focusing on efficiency, thermal behavior, and electromagnetic compatibility.
Building on these results, a system-in-package (SiP) concept based on a four-layer PCB embedding approach was developed. Critical low-profile components were integrated into inner layers to minimize overall module height. An optimized stack-up design and the targeted use of thermal vias enabled efficient heat dissipation. Several design variants were implemented to systematically investigate trade-offs between switching frequency, efficiency, thermal performance, and electromagnetic compatibility.
Experimental results indicate that, with the miniaturized embedded DC-DC converter modules, efficiencies of up to more than 85% can be achieved under nominal operating conditions, while maintaining a total module height of less than 6 mm. EMC measurements confirm compliance with relevant aerospace standards. In addition, yield and failure analyses provide valuable insights into process-related challenges and optimization potential toward future series production.
The presented results highlight the potential of PCB embedding technology as a key enabler for highly integrated, high-performance power supply modules in aerospace and other space-constrained applications.

Quasi-Monolithic Integration (QMI) is a wafer-level semiconductor integration technique that enables chiplets with different functions, sizes, process flow and substrate materials to be integrated on a single substrate.

In brief, the monolithic integration approach is a bottom-up technique, that all the components (transistors, capacitors, etc.) of a circuit are directly fabricated on a single wafer. Analogously, in QMI the chiplets (sensors and ASICs) are integrated and connected at the wafer-level so that they can work together as if within a single monolithic system. QMI effectively addresses limitations commonly encountered in monolithic integration, particularly flexibility and scalability. The chiplets integrated in QMI are allowed to be independently developed and manufactured using different process technologies and can be freely combined and reconfigured within the system as needed. Moreover, the impact of failures in single modules on overall system performance and yield during fabrication can be mitigated by using best known die (BKD).

In QMI, the gap between chiplets and the pocket wafer can be approximated as a deep trench with very high aspect ratio (AR) (max. 100:1 depending on chip size). This case can pose severe challenges for conventional gap-filling processes (chemical vapor deposition (CVD)) and such high AR trench filling is rarely reported in literature. Although atomic layer deposition (ALD) can principally reduce voids via self-limiting surface reactions and high conformality, its low growth per cycle results in excessively long deposition time and high costs at the required film thicknesses. The deposition rate of our ALD process can be approximately seen as 0.5 nm/min (about 0.1 nm/cycle, one cycle is about 12 s). For 1 µm deposition our ALD process needs more than 33 hours.

Chemical vapor deposition (CVD) is a diffusion-limited process compared to ALD. The Chiplets integrated into the pocket wafer have a limited thermal budget up to 400°C. Plasma enhanced CVD with deposition temperature 400°C seems to be the most suitable process for our case. However, the deposition rate of PECVD at Trench top is higher than it at the bottom. So, high AR gap-filling with PECVD caused the premature pinch-off at top and there was a large internal void.

Our goal is to optimize deposition strategies that balance void control with time efficiency. We will evaluate two approaches. First, a deposit–sputter–deposit (DSD) sequence: intermittent sputter-etch steps are introduced to reopen partially closed trench top and remove overhangs, thereby restoring reactant access deeper into the trench during subsequent PECVD cycles and reducing void volume. Second, pulsed CVD designed for high-AR structures: by temporally modulating precursor delivery and pressure, pulsed CVD aims to reduce diffusion-limitation relative to continuous CVD, while maintaining significantly higher deposition rates than ALD. And we should make sure that our approaches would not damage the chiplets by using too high temperatures (< 400°C) or attack chiplets while reopening the trench.

We want to identify an approach that achieves the most conformal trench filling with an acceptable void level to hold the chiplets in shape of their pockets, and substantially reduced processing time relative to ALD.

Energy-autonomous sensing platforms are increasingly required for scalable smart systems integration in smart mobility, infrastructure health assessment, emerging Industry 5.0 applications. While energy harvesting technologies have matured at component level, their reliable deployment in real-world environments remains limited by packaging and heterogeneous integration challenges and by energy conversion efficiency. This work describes their packaging challenges and introduces an “Energy-Source-in-Package” (eSiP) architecture that could integrate energy harvesting, power management, storage, sensing, and communication into compact, robust modules suitable for harsh environments.

The proposed methodology emphasizes system-level co-design where packaging is treated as an active functional element influencing electrical performance, mechanical coupling, thermal transport, and long-term reliability. Multi-modal energy harvesting strategies—including piezoelectric, triboelectric, thermoelectric, and electromagnetic mechanisms—are analyzed from a heterogeneous integration perspective. Key packaging challenges include impedance matching across heterogeneous materials, integration of flexible energy harvesters with rigid electronics, encapsulation strategies balancing environmental protection with energy transfer efficiency, and scalable interconnect approaches compatible with industrial assembly workflows.

A central contribution is the identification of packaging-induced constraints that directly affect energy harvesting performance and system durability, as seen in our industrial prototypes tested across multiple application domains and technology readiness levels - thermoelectric harvesters integrated into hydraulic equipment monitoring systems, kinetic energy harvesters for smart tire applications. For example, triboelectric and piezoelectric devices introduce unique trade-offs between exposure to environmental stimuli and protection against moisture ingress, mechanical fatigue, and charge leakage. Flexible and stretchable harvesting structures require novel interconnect solutions capable of sustaining repeated deformation without electrical degradation. Thermal and mechanical design considerations are shown to significantly impact energy conversion efficiency, highlighting the need for co-optimization of mechanical design and electrical architecture. Lessons learned demonstrate that packaging architecture is a primary determinant of scalability and industrial viability.

The paper further discusses materials selection, encapsulation methodologies and the need for pathways toward standardized packaging workflows aligned with European semiconductor and smart systems initiatives. Future directions include co-packaged edge AI electronics, advanced energy storage integration, and manufacturing-ready design methodologies enabling maintenance-free sensing infrastructures. The presented examples highlight how packaging decisions directly influence system efficiency, durability, and technology readiness level (TRL) progression.

Structural electronics represent a paradigm shift in system integration, where load-bearing materials simultaneously function as electronic substrates. While conventional PCB materials such as FR-4 are non-structural, emerging applications in aerospace, mobility, and smart infrastructure demand lightweight structural components capable of supporting embedded sensing and copper-based circuitry.

This commercial white paper examines the feasibility of natural-fiber biocomposite substrates for structural electronics applications, focusing on mechanical performance, thermal compatibility, and copper lamination constraints.

Baseline hemp-fiber composite panels were mechanically characterized using ASTM D790 (flexural) and ASTM D3039 (tensile) methods. Flexural strength values in the range of 80–90 MPa and flexural modulus values near 4 GPa were observed for ~2.5 mm ASTM test coupons. While these values demonstrate promising stiffness-to-weight ratios compared to conventional polymeric substrates, copper lamination trials revealed critical limitations in PLA-based matrix systems. Thermal softening during lamination resulted in dimensional instability and surface degradation, preventing reliable PCB-style processing.

These findings highlight a key commercial bottleneck: structural stiffness alone is insufficient for electronics compatibility. Substrate systems must satisfy simultaneous requirements for:

• Controlled coefficient of thermal expansion (Z-CTE compatibility)

• Thermal resistance during copper lamination

• Fire retardancy (preferably phosphate-based organic systems)

• Thickness constraints (≤2.5 mm for PCB process compatibility)

• Mechanical durability for structural use

This paper outlines the engineering boundary conditions required for viable biocomposite structural electronics substrates and proposes a development pathway involving matrix modification, increased fiber volume fraction, and hybrid composite architectures.

Rather than positioning biocomposites as drop-in replacements for FR-4, this work frames them as a new substrate class requiring co-design between materials engineering and electronics packaging.

The commercial opportunity lies in lightweight, sustainable substrates for aerospace interiors, smart panels, and embedded sensing systems where structural and electronic functions converge.

For applications such as high-speed transmission, 5G communication, HPC for AI, and new optical devices, a substrate that does not absorb moisture, has a small CTE, and has less warpage, the Glass core is required. This presentation will introduce the trends in Glass PKG technologies over the past decade while reviewing a very large number of technical papers logs. Furthermore, it will be introduced Glass package applications, and key technologies that will be required in the near future.

Topics

- Glass PKG history logs with technical papers, conference, and trends

- Glass PKG applications

- Glass PKG strong area

- Glass TGV metallization

For applications such as high-speed transmission, 5G communication, HPC, and new optical devices, a substrate that does not absorb moisture, has small a CTE, and has less warpage is required. In recent years, the development of methods for forming through-glass via (TGV), which are attracting attention as next-generation semiconductor packaging technology, has become increasingly important. Going forward, there will be an increasing demand for TGV with small via size, fine pitches, and high aspect ratios. Here report that direct drilling of ultra-high aspect ratios is possible in a single shot without an etching process to form high quality 1 um diameter TGV. This was achieved by combining a single shot GHz burst-mode ultrashort pulse laser consisting of an ultra-high repetition rate laser pulse train with an intra-pulse interval on the order of several hundred picoseconds with a Bessel beam.