Conference Agenda

This extended abstract studied the use of spin-on-glass (SOG) for micro-transfer-printing (µTP), as an alternative to conventional polymeric adhesive such as BCB and Intervia. Once cured, SOG behaves as transparent oxide layer and can be suitable for rugged environments. The authors demonstrated the µTP of both 200nm thick lithium niobate film and 3.2um thick a-Si cladded lithium niobate chiplets on SOG layer.

Adhesives has a central role into chip assembly, where they need to provide a reliable and stable interface between the chips the substrate. Adhesive does not only provide mechanical stability to the assembly but can also provide electrical and thermal connections. To add different functions to the adhesive layer different types of particles are mixed into the adhesive. In this work polymer spheres with and without Ag-metallization have been mixed into an epoxy resin to create Isotropic Conductive Adhesives (ICAs) and Non-Conductive Adhesives (NCA). These adhesives have been used for assembling dummy silicon dies to PCBs (ENIG and solder stop surface) which in turn have been shear- tested as bonded and after thermal aging. For the dies bonded to the solder stop the fracture mainly happened between the solder stop and the core of the PCB. For dies bonded to ENIG the fracture in general was cohesive in the adhesive with shear-strength above 30 MPa for four of the adhesives. Only the 10 µm N adhesive with uncoated polymer spheres (PS) and the Loctite Ablestik reference was measured to significantly lower shear-strengths.

Abstract— This paper presents a low-temperature curing process for temporary bonding adhesives enabling full B-stage curing at a thermal budget below 100 °C. The proposed approach prevents reflow or degradation of low–melting-point solder alloys, such as indium-based compounds, allowing their integrity to be preserved during temporary bonding, debonding, backside silicon interposer thinning, and BEOL processing.

I. INTRODUCTION

Quantum computing represents a promising direction for continued scaling beyond conventional CMOS, enabling the solution of computational problems with significantly increased complexity. Applications include quantum chemistry, materials science, battery development, catalyst optimization, drug discovery, and cryptography. As quantum processors begin to be deployed in hyperscale environments—such as IBM platforms and Google’s demonstrated 53-qubit processor (Fig. 1)—a key challenge is the integration of a sufficient number of qubits operating in parallel to improve computational accuracy and reduce error rates.

Quantum systems typically require cryogenic operation, which imposes strict constraints on power consumption and thermal budgets. Consequently, a large number of redundant qubits, low-power control electronics [3], and high-density interconnect architectures are required, as illustrated in Fig. 2 (courtesy of H. Bluhm [4]). These requirements significantly limit allowable backend processing temperatures, particularly when low–melting-point materials such as indium-based solders are employed.

II. EXPERIMENTAL RESULTS

Low-temperature temporary bonding experiments were performed using an indium-bumped silicon interposer bonded to a glass carrier with Brewer Science BrewerBond C1301-50 adhesive and BrewerBOND T1107 as a release layer. The process flow is shown in Fig. 3. A hybrid UV-assisted curing process with a maximum temperature of 90 °C was employed.

Film thickness measurements demonstrated a coating uniformity of 3% across the wafer (Fig. 4). Fourier-transform infrared (FTIR) spectroscopy confirmed identical cross-linked polymer structures when comparing the low-temperature UV-assisted cure with a reference process cured at 300 °C, indicating successful full B-stage curing.

Mechanical debonding was performed using a SUSS XBC300 system. Post–B-stage cleaning results are shown in Fig. 5, comparing samples processed using a standard curing approach and the hybrid curing method. Cleaning evaluations indicated that, relative to the standard process, additional cleaning rework was required for samples subjected to hybrid curing, suggesting a modified adhesive hardening behavior. However, the application of an additional oxygen plasma cleaning step enabled complete removal of residual adhesive. Further optimization of the cleaning process is ongoing to achieve single-step adhesive removal.

Backside processing following temporary assembly and hybrid curing is currently under evaluation.

Acknowledgment

Authors want to acknowledge Brewer Science for their support and their proactive interactions to help develop this concept.

References

[1] Ryan Mandelbaum, 12 Nov 2025, https://www.ibm.com/quantum/blog/qdc-2025

[2] F. Arute et al., “Quantum supremacy using a programmable superconducting processor”, Nature volume 574, pages505–510 (2019)

[3] M. Veldhorst et al., “Silicon CMOS architecture for a spin-based quantum computer”, Nature Communications 8, 1766 (2017)

[4] Hendrick. Bulum, Quantum Computing Concepts, Status quo and challenges ahead, 71st Annual IEEE International Electron Devices Meeting., December 6-10, 2025, San Francisco,USA

Optical read out systems guarantee higher accuracy, higher signal to noise ratio and an extremely high bandwidth compared to other read out mechanisms (e.g. capacitive, piezoresistive). The main drawback of such a systems is the requirements in terms of accuracy in the assembly.

An advanced active alignment process to align a constallation of light source and detectors and the target defractive element will be discussed. The diffractive element need to be placed at a specific distance and its position is oprimized based on live monitoring of the light detectors. The positions and rotation of the element will be then locked with a UV curable adhesive.

Such a process could enable advanced MEMS with optical readout systems for future applications to be more available and cheap, and outperforming conventional electrostatic MEMS sensors.

The increasing power density and miniaturization of certain electronic devices demand lightweight heat spreaders that offer high thermal conductivity while maintaining electrical insulation. This study compares two electrically insulating heat spreading solutions: (i) a highly filled hexagonal boron nitride (hBN)–polymer composite film serving as an intrinsically insulating heat spreader, and (ii) a graphene-assembled film combined with a Kapton insulating layer. Custom fabricated hBN films (~200 µm thick) with strong in plane alignment and ~93 wt% hBN content were characterized using Scanning Electron Microscopy (SEM), thermo-gravimetric analysis (TGA), and electrical breakdown voltage measurements. Both heat spreader configurations were experimentally evaluated under identical thermal loading using a customized thermal test rig, complemented by numerical modeling to assess the influence of lateral dimensions. Experimental results show that for larger lateral sizes (40 mm diameter), the graphene/Kapton laminate achieves lower heater temperatures and reduced thermal resistance due to the high in plane thermal conductivity of graphene-assembled films. However, modeling indicates that as the heat spreader diameter decreases, the performance of the graphene/Kapton laminate degrades more rapidly, whereas the hBN-based film becomes comparatively more effective due to its superior through plane heat transfer capability. Electrical testing further confirms that the hBN-based heat spreader shows significantly higher partial discharge inception voltage (PDIV) and surface flashover voltages. These findings underscore the critical role of anisotropic thermal transport and lateral size in the design of electrically insulating heat spreaders for advanced power electronics thermal management.