Conference Agenda

In recent years, Sb₂Se₃ has been identified as an ideal phase change material for phase modulation of light because it exhibits no intrinsic absorption losses (k<10^-5) in both amorphous and crystalline phases and an index contrast of ∆n = 0.77 (n_amorph = 3.285 and n_crys = 4.05) over telecommunication transmission band [1]. Also, the crystallization and amorphization temperatures of Sb₂Se₃ are 200ºC and 620ºC, respectively, comparable to those of Ge₂Sb₂Te₅ (GST) which is the most commonly used phase change material (T_crys = 140ºC and T_amorph = 550ºC) [2]. Furthermore, it is known that Sb₂Se₃ supports multilevel operation. The bidirectional multilevel operation of Sb₂Se₃ via a single-step partial crystallization and/or single-step partial amorphization scheme has been realized previously [3-4]. Quasi-continuous multilevel phase modulation has been achieved by controlling the programming energy (e.g., by adjusting the excitation pulse amplitude and width) [3-4] and engineering the temperature profile across the heater [4].

On-chip one-dimensional (1D) metasurfaces provide an innovative means of control over the diffraction and interference of light [5]. In this work, highly adaptive optical routing of guided waves is enabled by on-chip programmable Sb₂Se₃ phase-change metasurfaces. Driven by Genetic algorithm optimizations, a programmable optical router is devised by integrating on-chip 1D metasurfaces [5] with ultralow-loss Sb₂Se₃ on the silicon-on-insulator platform. The on-chip optical routing is achieved by adjusting the refractive index of the Sb₂Se₃ inclusions of the on-chip 1D metasurfaces (that is realizable by partial crystallization of Sb₂Se₃). This is an alternative method for defining the light flow to programmable on-chip cascaded interferometers and photonic meshes, with much smaller footprint and nonvolatile operation.

Fourier optics, besides providing a reasonable model of electromagnetic wave propagation in many applications, presents very computationally-efficient formulations of diffraction by exploiting fast Fourier transforms (FFTs) [6]. This has made Fourier-optics very ideal for incorporating into gradient descent procedures and/or performing real-time optimizations [6]. Our investigations, however, demonstrate that the combination of Fourier-optics with gradient-based optimizations lacks sufficient accuracy for the design and optimization of photonic devices. The combination of a full-wave electromagnetic solver that has the highest degree of accuracy, with gradient-based optimization methods, on the other hand, is restricted by the difficulty in obtaining the gradient information on a physical device [7]. In this article, the Lumerical 2.5D varFDTD solver which accurately and quickly can model the propagation of light in planar integrated optical systems on the scale of hundreds of microns [8] is incorporated into the Genetic algorithm to design the on-chip programmable optical router based on integrated one-dimensional Sb₂Se₃ phase change metasurfaces with the desired input/output routing. The effects of various Genetic algorithm hyper-parameters like partial reinitialization, population size and the number of generations in each optimization are also discussed. Finally, the presented design approach is compared to gradient-based methods combined with Fourier-optics. Supported by our results, the combination of the genetic algorithm with 2.5D FDTD simulations provides a more accurate, yet nearly fast approach to optimize the optical devices, compared to the gradient-based optimization methods relying on Fourier-optics models [9-10].

We describe the design and fabrication of silicon nanowire (SiNW)-based nanosensor devices for detecting explosives compounds. The SiNW-based nanosensor was fabricated using UV-photolithography and electron-beam thermal evaporation. Various parameters and procedures were optimized during the fabrication process. The SiNW was prepared and functionalized with triethoxysilylbutyraldehyde (TESBA) through self-assembly via covalent interactions. After the interaction, sensitivity studies were performed using explosive materials as the target detection molecule. The electrical response and sensing characteristics of the SiNW-based biosensor devices were measured using current-voltage (IV) analysis.

In recent decades, humanity has faced various global challenges that impact all living beings' economies, health, and survival. Pollution and access to soil and the environment are among the five most pressing issues. To tackle these challenges, numerous research groups worldwide have concentrated on developing innovative materials at various scales for detecting hazardous chemicals in soil, air, and water. 4-Nitrophenol (4-NP) is widely used in the pharmaceutical, leather, dye, and agrochemical industries. However, 4-NP is one of the most toxic and hazardous phenolic compounds, capable of causing lasting harm to humans, animals, and plants. It can irritate the skin, eyes, and respiratory system and may also adversely affect the liver and kidneys in humans. The United States Environmental Protection Agency (US EPA) has classified 4-NP as a priority pollutant that must be regulated in soil and the environment due to its significant toxicity; the maximum allowable concentration should remain below 0.43 μM. Additionally, the high stability and low biodegradability of 4-NP make it extremely difficult to remove from the environment. Electrochemical methods and high-performance liquid chromatography are employed to detect trace amounts of 4-NP. These methods are expensive, complex, and not easily accessible. There is increasing interest in developing new analytical tools for detecting 4-NP, underscoring the urgent need for straightforward, affordable, and rapid methods to identify trace levels of these compounds. In this regard, developing simple, reliable SiNW-based biosensor devices for detecting 4-NP addresses this urgent need and potentially significantly impacts environmental monitoring and protection.

The fabricated sensor array was conjugated with TESBA through self-assembly via covalent interaction. The SiNW surface was modified through siloxane (Si-O-Si) linkages, with the hydroxyl group facilitating the conjugation. The anti-TNT was immobilized on the TESBA functionalized SiNW sensor array using covalent interaction with the help of the hydroxyl group. The conjugated sensor array was used for the detection of 4-NP. The sensor array's electrical response and sensing behavior were analyzed using IV (current-voltage) measurement in the presence of 4-NP. Various spectroscopic and microscopic techniques examined the sensor array, functionalization, and sensing characteristics.The prepared SiNW observed an average dimension of 50 nm wide and 13.6 um long. From the analysis, SiNW-based nanosensor array bridged silicon nanowires between the chromium/gold metal layers. The results were compared with microscopic images which indicate that the fabricated sensor array contains no defects.

In recent years, there has been a big progress in artificial intelligence (AI) and high-performance computing (HPC), that have profoundly impacted the semiconductor industry. This progress has driven important innovations in hardware, particularly through the evolution of semiconductor manufacturing nodes, chiplet architectures, advanced packaging (AP), and high-speed interconnects. The continuous pursuit of higher computing power, improved performance, and enhanced system efficiency has boosted AP technolog families—such as Fan-Out, Flip-Chip, and 2.5D/3D —beyond their traditional limitations in form factor, bandwidth, manufacturability, and cost.

A critical challenge in this evolution lies in IC substrates, the foundational layer of advanced packages. The growing demands of AI workloads have directly influenced IC substrate development, necessitating improvements in line/space (L/S) scaling, larger form factors, mechanical stability, and the adoption of novel core materials. Among emerging solutions, glass core substrates (GCS) have gained attention as a promising alternative to conventional organic build-up substrates, offering many advantaghe such as superior dimensional stability, thermal conductivity, and electrical performance. These advantages enable finer interconnects and larger package sizes, which are critical for next-generation AP and HPC applications and can be also important for the Co-Packaged Optics (CPO).

However, the transition to GCS introduces several manufacturing challenges. Key bottlenecks include Through-Glass Via (TGV) fabrication, which requires precise laser drilling and metallization while minimizing defect formation, as well as surface chemistry optimization for reliable copper adhesion. Additionally, challenges related to the coefficient of thermal expansion (CTE) mismatch, warpage, and large-area glass handling must be addressed to enable scalable production. The adoption of GCS also necessitates advancements in panel-level manufacturing equipment to accommodate the unique characteristics of glass substrates.

This paper explores the ongoing efforts by IC substrate manufacturers to meet evolving industry requirements, the emergence of GCS as an emergent technology, and the key bottlenecks that must be overcome for a wider adoption. As glass substrates gain traction, particularly for high-performance AI and HPC applications, their potential to enable next-generation chip-to-chip interconnects and high-density redistribution layers (RDLs) is increasingly evident.

This study demonstrates the impact of nano-structured silicon surfaces on the performance of reactive multilayers (RMLs) bonding as a possible substitute for adhesion or solder layer. One of the tested structures are black silicon surfaces fabricated by reactive ion etching (RIE), which were thermally oxidized for enabling a self-propagating reaction. A previous study mentioned the significance of structure density for improving adhesion of reacted material. Hence, the structural density was systematically analysed using top-view scanning electron microscopy (SEM) combined with image processing methodologies, including binarization and the watershed algorithm, providing a robust quantitative framework for assessing surface morphology. In parallel, deep reactive ion etching (DRIE) was employed to produce silicon grass structures of 8 µm height, which proofed to reduce heat loss during reaction, as well as improving mechanical performance of the reacted material. Thus, enabling a self-propagating reaction of deposited reactive material, despite quenching of the same RML composition on bulk silicon. The Al/Ni RMLs had a total thickness of 5 µm, a bilayer thickness 50 nm and a 1:1 atomic ratio between Al:Ni. This approach of high and thin structures enabled the elimination of thermal insulation layers and obviated the need to increase RML thickness by mitigating heat dissipation through the substrate. The unique bending behaviour of the silicon grass structures during reaction effectively reduced stress transfer to the bulk substrate, further enhancing adhesion of the reacted RMLs.

The bonding performance of these two structured surfaces were evaluated using two configurations: (1) silicon-to-silicon bonding, employing 525 µm silicon wafers with a 1 µm thermal SiO₂ layer, metallized with 50 nm Ti, 100 nm Au, and either a 1 µm or 2 µm thick layer of Sn. (2) silicon-to-low-temperature cofired ceramics (LTCC), comprising six layers of DuPont 951 PX tapes with a 15.9 µm AgPd or AgPd/SAC 54 µm thick metallization layer. Bonding tests were conducted under a pressure of 10 MPa applied on a 1 cm² area. The reaction of the RMLs on the structured surfaces were initiated by spark ignition. The results confirmed successful bonding for the silicon-to-silicon configuration, attributed to a successfully established reactive bond between the two chips. However, while initial adhesion was observed in the silicon-to-LTCC bonds, they failed in most cases, indicating a need for further optimization of the interface chemistry and mechanical compatibility. Pull tests performed on the silicon-to-silicon bonds demonstrated high bond strength, underscoring the effectiveness of the structured surfaces in achieving robust and reliable adhesion.

This work establishes a foundational strategy for material reduction by engineering silicon surface structures to enhance reactive bonding processes, presenting implications for applications requiring localized heating, material-efficient bonding solutions. Future studies should focus on identifying more surface structures and their impact on the reaction, as well as including interfacial strategies on the LTCC bonding like laser ablation to improve the performance.

Power electronic components play a major role in many industries with applications in automotive, aerospace, and railway transportation. With the increasing demand, reliability and efficiency constraints that come from the growth in lifetime expectation and safety requirements are major challenges of these devices.

Thermal cycling is a common phenomenon occurring in power electronic (PE) modules during operation and results in failure due to a mismatch of the Coefficient of Thermal Expansion (CTE) between interconnecting components with different materials. One such failure is due to the increase in junction temperature of the module triggering degradation. A common type of failure found in PE modules is from the separation of layers known as delamination. This paper proposes a concept that helps in minimizing delamination propagation after a certain threshold by giving feedback on reducing input conditions.

The power electronic module investigated is a MOSFET equipped with silicon carbide (SiC) semiconductor that operates in high temperature and high frequency used in automotive applications. The Accelerated aging test is widely recognized as the most common and efficient method for the determination of the reliability of a PE component. Active power cycling test which is one of the prominent types of accelerated aging test is used for both experimental validation and simulation purposes.

A 3D finite element (FE) sub-model is developed using ANSYS software to simulate the electrothermal behavior of the PE module. Percentage of total delaminated area in die attach solder layer is considered as a criterion for finite element simulation and the resulting junction temperature is studied. The obtained junction temperature of the module is compared to that of the experimental test and certain adjustments in the boundary condition of the FE model are initiated as part of the calibration. Criteria is defined in such a way that a 20% increase in thermal resistance and a 5% increase in drain-source voltage enable determination of the current state-of-health (SoH) of the module. With the determination of SoH, the remaining useful life (RUL) of the module can be obtained.

The next phase involves the possibility of the extension of service life by adjusting operating loads in such a way that it would further reduce the junction temperature. In Design of experiment (DoE) study of the calibrated model, various simulations were conducted with different input conditions such as current as loading condition, coolant temperature for environment condition and delamination as damage condition are simulated and resulting junction temperature, thermal resistance, and drain-source voltage are investigated. From the DoE study, the response surface as a compact model is developed that acts as a surrogate model providing efficient and instant prediction of system behavior that can be used for monitoring the failure risk of the module.

The precision and reliability of MEMS devices critically depend on the quality of their hermetic sealing processes, particularly in applications requiring stringent vacuum conditions. In order to maintain optimal device functionality over extended periods, it is essential to achieve high vacuum levels with minimal residual gas contamination. This work presents advancements in MEMS packaging technology enabled by a redesigned dual-chamber thermal getter system and the introduction of a novel tooling material, which together contribute to improved sealing precision and long-term vacuum stability.

The SRO Getter system is specifically designed to both hermetically seal MEMS packages and activate the getter material within the package, ensuring optimal environmental conditions for device longevity. The enhanced system architecture isolates getter activation from package sealing, enabling independent optimization of process parameters. This separation allows for more controlled processing conditions, reducing unintended interactions between different stages of the packaging process. The incorporation of the new tooling material significantly improves temperature uniformity during thermal processing, ensuring precise heat distribution across the package. Improved thermal consistency reduces localized overheating and thermal gradients, which are critical factors in ensuring the integrity of MEMS devices. Additionally, an active cooling system has been integrated to speed up cooling in high-vacuum conditions, allowing for better control over intermetallics formation. By managing cooling rates more effectively, the system mitigates material diffusion effects that could otherwise impact the mechanical and electrical properties of the final sealed package. These improvements result in better control over the sealing process, increased yield, and improved reproducibility.

The rapid evolution of information technology—driven by artificial intelligence, cloud computing, search engines, e-commerce, and Big Data—has spurred increasing demand for new application areas. Photonics remains central to expanding global communication networks, yet there is growing pressure to develop highly integrated solutions rather than rely on separate components. While traditional microelectronics-photonics hybrid integration methods, such as mass-reflow and thermo-compression bonding, do mitigate thermally induced warpage through uniform pressure, these approaches are often difficult to implement effectively in silicon photonics. Consequently, the field now demands more advanced techniques that ensure precise alignment of photonic devices, faster assembly, and consistent reproducibility on high-volume production scales.

In this context, Laser-Assisted Bonding (LAB) has emerged as a promising alternative to existing bonding methods, offering higher speed and improved energy efficiency. Its primary advantage lies in the localized application of heat, which minimizes thermal stress and reduces warpage—an especially critical consideration in photonic integration, where even slight structural changes may cause optical axis misalignment, elevated insertion or signal losses, and potential component damage.

To achieve the level of alignment required, we implement a through-silicon imaging method with bottom illumination. This arrangement makes it possible to visualize the waveguides simultaneously on both the semiconductor chip and the silicon substrate, thereby enabling advanced image recognition-based alignment strategies for optimal results.

In a practical demonstration, we employed LAB to mount a 1×1 mm III–V multichannel chip onto a silicon photonic circuit. Through localized heating, we quickly raised the photonic circuit’s temperature above the solder’s melting point and formed bonds meeting the shear bond force specifications outlined in MIL-STD-883H. Crucially, this bonding process decreases thermally induced stress and curtails warpage on the bonded surfaces. Validating LAB’s functionality in this setting also underscores its potential to enhance overall yield in photonic integration.

Notably, LAB enables both rapid bonding and waveguide alignment through bottom illumination/irradiation and real-time through-silicon imaging—an essential requirement for effective photonic integration. Taken together, these findings represent a significant step forward in photonic integration technologies, highlighting LAB’s capability to address the expanding and increasingly stringent needs of this rapidly developing sector.

This work was supported by Business Finland under project SmartFab (Advanced Automated Manufacturing Tools for Fabrication of Photonics Components and Systems, Joint action identifier 5100/31/2022) and Academy of Finland through Photonics Flagship program PREIN (Photonics REsearch and INnovation) #320168.

The constantly shifting landscape of information technology—spurred by advancements in artificial intelligence, cloud computing, search engines, e-commerce, and Big Data—has intensified the demand for new application spaces. Although photonics is instrumental in broadening worldwide information networks, contemporary requirements favor tightly integrated solutions over standalone components. This shift necessitates advanced methodologies capable of delivering stringent alignment tolerances for photonic devices, rapid assembly, and consistent reproducibility at volume. Precise alignment is paramount, since even minor deviations can significantly decrease optical coupling efficiency, device performance, and productivity in high-throughput manufacturing.

A key strategy for addressing these challenges lies in Short Wavelength Infrared (SWIR) imaging, which exploits silicon’s transparency at wavelengths above 1 µm to enable real-time observation of bonding interfaces through the silicon substrate—using a bottom-illumination architecture. As silicon photonics gains traction, achieving waveguide-to-waveguide alignment before and controlling it after assembly to submicrometer accuracy becomes increasingly critical, preventing unacceptably high coupling loss. In this work, we showcase the development of a Through-Silicon Microscopy (TSM) System that unites an infrared imaging channel with a laser-irradiation channel for efficient and energy-effective Laser-Assisted Bonding (LAB) assembly process. By combining classical optical system design principles with cutting-edge imaging approaches—such as computational reconstruction algorithms and phase microscopy—we established optimal system parameters through finite element and ray-tracing simulations, while experimental validations confirmed robustness under diverse operating conditions. The result is a powerful platform for next-generation photonic integration, delivering precise, high-throughput characterization and alignment with minimal thermal-induced warpage.

Central to this design is a cost-effective TSM setup featuring bottom illumination/irradiation architecture and a dedicated laser channel for LAB. This configuration supports a rapid, energy-efficient, and flexible bonding procedures, simultaneously ensuring sub-µm alignment for heterogeneous photonic integration. Overall, our findings underline the versatility and scalability of this approach, positioning it as a compelling solution for contemporary photonics challenges.

This work was supported by the Academy of Finland (project no. 336357, PROFI 6 - TAU Imaging Research Platform)