Conference Agenda

Today, most of the package substrates driven by AI (artificial intelligence) are made by the 2.5D IC integration. In general, for 2.5D, the chips and high bandwidth memories (HBMs) are supported by a TSV-interposer and then solder bump and underfill on a build-up package substrate. However, because of the ever-increasing size of the TSV-interposer, the manufacture yield loss of the TSV-interposer is becoming unbearable. In the past few years, 2.3D IC integration is getting lots of traction. The motivation is to replace the TSV-interposer with a fan out fine metal L/S redistribution-layer (RDL)-substrate (or organic-interposer). In general, for 2.3D, the package substrate structure (hybrid substrate) consists of a build-up package substrate, solder joints with underfill, and the organic-interposer. Today, 2.3D is already in production. During IEEE/ECTC 2023, TSMC published two papers on replacing the large-size TSV-interposer by LSIs (local silicon interconnects, i.e. Si bridges) and embedding the LSIs in fan-out epoxy molding compound and RDL-substrate. TSMC called it CoWoS-L. Very recently, since Intel’s announcement on the glass core substrate for their one-trillion transistors to be shipped before 2030, glass core substrate has been a very hot topic. In this lecture, the introduction, recent advances, and trends in the substrates in 3.5D IC integration, 3D IC integration, 2.5D IC integration, 2.3D IC integration, 2.1D IC integration, and fan-out RDL substrate, Si-bridge substrate, CoWoS-R, CoWoS-L, co-packaged optics substrate, and glass core substrate for high-performance computing (HPC) driven by AI will be discussed.

Author Bio

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 515 peer-reviewed papers (375 are the principal investigator), 40 issued and pending US patents (25 are the principal inventor), and 23 textbooks (all are the first author), e.g., Chiplet Design and Heterogeneous Integration Packaging (Springer, 2023). John is an Fellow of IEEE, ASME, and IMAPS, and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share. He received many awards, e.g., the IEEE Components Packaging and Manufacturing Technology Field Award and ASME Worcester Reed Warner Medal.