IEEE ESTC 2024
September 11–13, 2024 | Berlin, Germany
Conference Agenda
Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).
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Agenda Overview |
| 8:00am - 2:30pm |
Registration |
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| 8:30am - 10:30am |
„IEEE EPS Heterogeneous Integration Roadmap“ (HIR) I Location: MOA 10-12 |
PDC: “Advanced Packaging for MEMS and Sensors” I Location: MOA 5 Course instructor: Horst Theuss |
PDC: “Automotive Electronics Reliability – Assurance Approaches and Challenges” I Location: MOA 4 Course instructor: Pradeep Lall |
PDC: “Flip Chip Fabrication and Applications“ I Location: MOA 3 Course instructor: Eric Perfecto |
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| 10:30am - 10:45am |
Break |
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| 10:45am - 12:45pm |
„IEEE EPS Heterogeneous Integration Roadmap“ (HIR) II Location: MOA 10-12 |
PDC: “Advanced Packaging for MEMS and Sensors” II Location: MOA 5 Course instructor: Horst Theuss |
PDC: “Automotive Electronics Reliability – Assurance Approaches and Challenges” II Location: MOA 4 Course instructor: Pradeep Lall |
PDC: “Flip Chip Fabrication and Applications“ II Location: MOA 3 Course instructor: Eric Perfecto |
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| 11:00am - 3:00pm |
Exhibition Setup Location: Atrium |
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| 12:45pm - 1:30pm |
Break |
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| 1:30pm - 1:45pm |
Opening Location: MOA 10-12 Opening remarks Tanja Braun General Chair IEEE ESTC2024 Welcome on behalf of the German Ministry for Education and Research (BMBF) Engelbert Beyer Deputy Director-General of Directorate 51, Technology-Oriented Research for Innovation, BMBF, Germany |
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| 1:45pm - 2:30pm |
Keynote 1 Location: MOA 10-12 "A Vision for Modular, Ubiquitous and Scalable Compute Systems" Bernd Waidhas Principal Engineer, Silicon Packaging Architecture, Intel |
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| 2:30pm - 2:40pm |
Room change |
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| 2:40pm - 3:55pm |
MIP1_Advanced Material Architectures for Interconnects Location: MOA 10-12 Chair: Glenn Hamilton Ross, Aalto University Solid-state Growth Kinetics of Compound Layers in Electroplated Cu-In Layer Systems 3:05pm - 3:30pm Superconducting Superlattice Interconnects for Cryogenic Systems 3:30pm - 3:55pm Aluminium-Aluminium Wafer Level Thermo Compression Bonding Using Thick Electroplated Aluminium Bonding Frames |
AP1_Advanced Substrates Location: MOA 5 Chair: Andreas Ostmann, IZM Development of Packaging Technology for 2.xD Advanced Packages; Fine Bump Interconnection, Fine Cu Wiring and Large Package 3:05pm - 3:30pm Advancing Chiplet Architecture Through Heterogeneous Integration on Laser-processed Glass Substrates 3:30pm - 3:55pm High Rate and Selective (Deep) Reactive-ion Etching Process for the Formation of High-density Vertical Interconnects into Dielectric Build-up Films |
Opto1_Photonic Module Packaging Location: MOA 4 Chair: Henning Schröder, Fraunhofer IZM Array Packaging with Integrated Mirrors for High Power Multi-chip UVC-LED Modules 3:05pm - 3:30pm Modular Integration of Quantum Cascade Lasers and Drivers in Glass Bench 3:30pm - 3:55pm Improving the Thermal Management of Power LED Arrays with Diamonds |
DTM1_Co-design and Modeling for Chiplets Location: MOA 3 Chair: Chris Bailey, Arizona State University Simulations of Wafer-to-wafer Bonding Dynamics and Deformation Mechanisms 3:05pm - 3:30pm Signal Integrity Optimization for CoWoS Chiplet Interconnection Design Assisted by Reinforcement Learning 3:30pm - 3:55pm Finite Element Analysis of Stress Variation of Hybrid Bonding During Miniaturization of Interconnects |
Power1_Electronics Measurement and Simulation Location: MOA 1+2 Chair: Aurelian Kotlar, Eberspächer Dynamic Calibration of Junction Temperature of SiC MOSFETs for Power Cycling 3:05pm - 3:30pm Contact Thermography – New Findings, New Ideas 3:30pm - 3:55pm Abrasion Characterization of Graphene-enhanced Thermal Interface Materials for Electronics Thermal Management Applications |
| 3:00pm - 8:00pm |
Exhibition Location: Atrium |
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| 3:55pm - 4:25pm |
Coffee Break & Exhibition Location: Atrium |
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| 3:55pm - 5:00pm |
Poster Session 1 Location: Atrium Chair: Karl-Friedrich Becker, Fraunhofer IZM Fabrication of Fine-Pitch Cu-Sn Microbumps Using Electroplating and Wet Seed Layer Etching Eclipse Versus Conventional Optical Choppers: Modeling and Analysis Development of HTC Tests on Module Basis Low-temperature Adhesive Wafer Bonding for Film Layer Transfer Adhesive Solutions for Closed Cavity Packaging Infrared Optical Solutions for Void Inspection of Bonded Wafers and Bonding Overlay Control Investigation of RF Characteristics of Chiplet to PCB Transitions for Advanced HPC Packaging Solutions Molding Process Simulation and Viscoelastic Model for Package Warpage Anticipation 2.5D/3D Chiplets Approach to Advanced Packaging Solutions Automatized Multi-objective Optimization for Reliability of Power Electronics Adhesion Layer Analysis by Spectroscopic Ellipsometry Inline Oxide Removal Through Openair-plasma to Solve Delamination and Improve Bonding in Electronics Heat Spreading in Uncovered Copper Sintered Die-Attach Layers Examined with Lock-In Thermography Evaluation of Mobile Data Center Cooling Performance Based on Embedded Cooling |
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| 4:25pm - 4:55pm |
Exhibitor Pitches Location: MOA 10-12 |
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| 4:55pm - 5:00pm |
Room change |
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| 5:00pm - 6:15pm |
MIP2_Advanced Interconnection Metallurgical Materials and Interconnects Location: MOA 10-12 Chair: Ali Roshanghias, Silicon Austria Labs GmbH Tuning of Copper Grain Size for Integration in Hybrid Bonding Applications 5:25pm - 5:50pm Fine Pitch Aluminum Hybrid Bonding at Wafer Level: Overcoming the Challenges in Plating, Passivation and Planarization 5:50pm - 6:15pm Surface Activated Bonding for Hybrid and All-metal 3D (AM3D) Interconnect |
AP2_Hybrid Bonding I Location: MOA 5 Chair: E Jan Vardaman, TechSearch International, Inc. Ultra Low Temperature Hybrid Bonding: Morphological and Electrical Characterizations 5:25pm - 5:50pm Overlay Scaling Error Reduction for Hybrid Die-To-wafer Bonding 5:50pm - 6:15pm Scatterometry Application on Cu/SiCN Surface Topography Towards High Volume Manufacturing |
Opto2_Heterogenous PIC Integration Location: MOA 4 Chair: Giovanni Delrosso, VTT Laser-Assisted Bonding of a Miniature Multichannel Laser Diode Chip to a Silicon Photonics Integrated Circuit with Through-Silicon Alignment 5:25pm - 5:50pm Over 100-GHz Bridge Chip Interconnection Between Photonic and Electrical ICs with a Heat-insulating Stress-relief Membrane Structure 5:50pm - 6:15pm Advanced Ultrathin Spray Coating Process Technology for Heterogeneous Integration Applications |
DTM2_Reduced Order Modeling for Advanced Packaging Location: MOA 3 Chair: Kshitij Anil Kolas, Fraunhofer ENAS Reduced-Order Modelling for Coupled Thermal-Mechanical Analysis and Reliability Assessments of Power Electronic Modules with Nonlinear Material Behaviours 5:25pm - 5:50pm Highly Efficient Modeling of Solder Balls and Their Visco-plastic Behavior Applying the Energy Conserving Sampling and Weighting Method 5:50pm - 6:15pm Coupled Electrothermal Analysis with Reduced Order Models for Optimizing GaN HEMTs Performance in Traction Inverters |
Power2_Power Semiconductor Packaging and Cooling Location: MOA 1+2 Chair: Gudrun Feix, ECPE European Center for Power Electronics Model-based Development to Improve Electrical and Thermal Performances for Robust Si Power MOSFETs Using Embedded Die Packaging Technology 5:25pm - 5:50pm Research on Ultra-compact 3D SiC Power Module for EVs with Double Layer Cooling Technology 5:50pm - 6:15pm An Introduction to Wire-bondless Discrete GaN Power Packages with Top-Side Cu Sinterconnects® |
| 6:15pm - 8:00pm |
Welcome Reception Location: Atrium |
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| 8:30am - 9:15am |
Keynote 2 Location: MOA 10-12 "Electronics Integration: Challenges in Computed Tomography Scanners" Dr. Michael Hosemann Head of Digital Electronics at Healthineers Computed Tomography Detector Center, Siemens |
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| 8:30am - 7:00pm |
Exhibition Location: Atrium |
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| 9:15am - 10:30am |
MIP3_Low-temperature Materials for Interconnects and Packaging Location: MOA 10-12 Chair: Hiroshi Nishikawa, Osaka University Low Temperature Die-attach Bonding Using Copper Particle Free Inks 9:40am - 10:05am Cu–(Sn–Bi) SLID Bond Microstructure Under Different Bonding Temperatures 10:05am - 10:30am Die Shear Strength of Au-In-Bi SLID Bonds at Elevated Temperatures |
AP3_Hybrid Bonding II Location: MOA 5 Chair: Rolf Aschenbrenner, Fraunhofer IZM High Precision Direct Transfer Bonding for Submicron Die-to-wafer in 3D/Heterogeneous Integration 9:40am - 10:05am Bond Strength Measurement for Wafer-level and Chip-level Hybrid Bonding 10:05am - 10:30am Optimization of Cu/SiCN Hybrid Bonding Process Using a Cohesive Zone Model |
AMT1_Innovative Assembly Processes Location: MOA 4 Chair: Attila Géczy, Budapest University of Technology and Economics Secondary Optics Assembly for Micro Concentrating Photovoltaics: A Parallelized and Scalable Approach 9:40am - 10:05am Massive Parallel Assembly and Interconnection for Micro-LEDs – a Technical Feasibility Study 10:05am - 10:30am Tape Frozen Detachment Process Using Freeze Chuck for Chip to Wafer |
DTM3_Reliability and Virtual Prototyping Location: MOA 3 Chair: Pradeep Lall, Auburn University Reliability Testing and Virtual Prototyping for Embedded GaN Power Modules in Automotive Applications 9:40am - 10:05am Fully Connected Neural Network (FCNN) Based Validation Framework for FEA Post Processing to improve SAC Solder Reliability Analysis 10:05am - 10:30am Re-Integrating a Reduced-Order Model into Finite Element Environment for Thermo-Mechanical Reliability Analysis in Microelectronics |
Rel1_Reliability Performance and Electromigration Behavior Location: MOA 1+2 Chair: Matthias Heimann, Siemens AG Electromigration Reliability of Cu3Sn Microbumps for 3D Heterogeneous Integration 9:40am - 10:05am Investigating the Failure Mechanisms of Electromigration and Copper Oxide Formation in Fine-pitch Cu RDL 10:05am - 10:30am Investigation of the Influence of Shear Height in the Wire Bond Shear Test |
| 10:30am - 11:00am |
Coffee Break & Exhibition Location: Atrium |
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| 10:30am - 11:45am |
Poster Session 2 Location: Atrium Chair: Karl-Friedrich Becker, Fraunhofer IZM Critical Parameters of Bond Strength Measurement on Wafer Bonding Investigating Competing Failure Modes in Microelectronics due to Temperature Variations (ΔT) Development and Characterization of a Chip-film Patch Interposer Integrating an Ultrathin Electrophysiology Chip Reliability Analysis of Surface Mount Interconnect Technologies Suitable for Temperatures up to 200 °C Using Polymer Paste as Dielectric Material for PCB Based Module-to-Module Sintering Non-phthalate and Biobased Plasticizers in Suspensions for Tape Casting The Potential of Machine Learning for Thermal Modelling of SiC Power Modules - A Review Simulation and Experimental Analysis of Thermomechanical Stresses Around Interconnects for W2W Hybrid Bonding RF Characterization and Analysis of Low-loss PCB Materials and Transmission Lines up to 110 GHz Bilayer Encapsulant for Lower Stress Moisture Protection Laser Assisted Bonding (LAB) Based Flip-chip Process for Fine Pitch Solder Bumps Device Using Laser Non-conductive Paste (NCP) Recycling SMD Components for E-Textile Fabrication: A Salt Spray Ageing Study Experimental Study on Reactive Joining Processes on LTCC Substrates Development and Realization of Plasma Activated Low Temperature SiOx-SiOx Fusion Bonding Based on a Collective Die-to-wafer Bonding Process A Novel 8GHz/50MHz Low Noise Dual Frequency PLL. Innovative Active Cell Balancing Circuit Using Common Capacitor for Energy Redistribution |
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| 11:00am - 12:15pm |
Emerging I_From Mounting to Recycling – Highlites from Emerging Technologies Location: MOA 10-12 Chair: Martin Oppermann, TU Dresden Feasibility of Micro-grass on Silicon Cap as An Alternative Antireflective Layer in Vacuum Packaging of Microbolometer Arrays 11:25am - 11:50am Biodegradable PCBs with PLA/flax Substrate: FTIR and SEM Analysis of Degradation 11:50am - 12:15pm A Novel Ultra-thin Dicing Die Attach Film for Various Dicing Processes |
AP4_Advances in WLP Technologies I Location: MOA 5 Chair: Rolf Aschenbrenner, Fraunhofer IZM Semi-Additive Fine Pitch RDL Litho-Process Development of 1000nm CD Using low-NA 300mm i-line Stepper 11:25am - 11:50am Study of Cross-contamination in Multi-chamber PVD Systems used for High-throughput Seed Layer Deposition 11:50am - 12:15pm Enhanced Defect Detection with Deep Neural Networks Post Wafer Bonding |
AMT2_Computer-aided Process Control Location: MOA 4 Chair: Erik Jung, Fraunhofer IZM Advancements in Epoxy Pattern Quality Checks: Harnessing Artificial Intelligence for Enhanced Low-Contrast Analysis 11:25am - 11:50am Dicing Lane Quality Quantification & Wafer Assessment Using Image Thresholding Techniques 11:50am - 12:15pm AI Deep-Learning Approach for Manufacturing Optimization During Chiplets and Heterogeneous Package Inspection |
DTM4_Device Level Modeling Location: MOA 3 Chair: Przemyslaw Gromala, Robert Bosch GmbH Latency Insertion Method for FinFET Simulation Incorporating Parasitic Source/Drain Resistances 11:25am - 11:50am CANCELLED: Adaptive Artificial Neural Networks for Power Loss Prediction in SiC MOSFETs 11:50am - 12:15pm Simulation Analysis on Thermal Performance of Lidless Fan-out Package |
Rel2_Package- and Board Level Moisture- and Thermal Stress-related Reliability Effects Location: MOA 1+2 Chair: Romuald Roucou, NXP Boundary Conditions for Reproducible and Comparable Condensation Tests to Prove the Migration Resistance of Assemblies 11:25am - 11:50am Analysis of LED Solder Joints During Combined Power and Thermal Cycling 11:50am - 12:15pm Analysis of Degradation Effects for Different Epoxy-based Molding Compounds (EMC) Under High Temperature Aging |
| 12:15pm - 1:45pm |
Lunch |
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| 1:45pm - 3:15pm |
Special Session Location: MOA 10-12 Chair: Steffen Kroehnert, ESPAT-Consulting Chair: Klaus Pressel, Infineon The Future of Packaging in Europe - Strategies and Funding for R&D and Manufacturing I IPCEI ME/CT and Pack4EU/ EU CHIPS ACT |
AP5_Advances in WLP Technologies II Location: MOA 5 Chair: Michael Schiffer, Fraunhofer IZM Package Assembly Design Kits (PADK’s) – The Future of Advanced Wafer-level Manufacturing 2:10pm - 2:35pm Fan-out Packaging Reaching New Heights: Market and Technology Overview 2:35pm - 3:00pm Optimizing Laser Direct Write for Fan Out Packaging |
AMT3_Process for Enhancement of Device Robustness Location: MOA 4 Chair: David Henry, CEA LETI Advanced Wafer Singulation Technique for Miniaturized Metal-oxide (MOX) Micro-hotplates Based Gas Analyzer 2:10pm - 2:35pm Characterizations of Metal-based Thermal Interface Materials (TIM) in a Singulated Flip Chip Ball Grid Array Package 2:35pm - 3:00pm Automated Highspeed Characterization of Optical Waveguide in large-format Glass Substrates |
Special Session Location: MOA 3 PUNCH - Photonic Packaging |
Special Session Location: MOA 1+2 Education I: The Education, Training and Qualification Offer for Sustainable Electronics |
| 3:15pm - 3:45pm |
Coffee Break & Exhibition Location: Atrium |
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| 3:45pm - 5:15pm |
Special Session Location: MOA 10-12 Chair: Klaus Pressel, Infineon Chair: Steffen Kroehnert, ESPAT-Consulting The Future of Packaging in Europe - Strategies and Funding for R&D and Manufacturing II IPCEI ME/CT and Pack4EU/ EU CHIPS ACT |
AP6_Challenges and Solutions for HI Location: MOA 5 Chair: Kay Essig, ASE Group Acoustic MEMS Packaging for Audio Micro-System Applications 4:10pm - 4:35pm IMC Assisted Die-bonding for Stacked Device Integration 4:35pm - 5:00pm High-throughput In-line SEM Metrology for Cu Pad Nanotopography for Hybrid Bonding Applications |
Emerging II Location: MOA 4 Chair: Martin Schneider-Ramelow, Fraunhofer IZM 10 Golden Rules of Chip- Package- Board Interactions Trench-Based Fully Integrated Capacitors for Power Delivery in Heterogeneous Integration Platforms Sustainable Temperature and Pressure Sensing Solution for Tire |
Special Session Location: MOA 3 Chair: Toni Mattila, Business Finland Quantum Computing |
Special Session Location: MOA 1+2 Chair: Jeffrey C. Suhling, Auburn University Chair: Klaus-Jürgen Wolter, TU Dresden Education II: t.b.c. |
| 5:15pm - 6:45pm |
Panel Discussion "Chiplet Architectures for Automotive: Package Options and Special Considerations" E. Jan Vardaman, TechSearch International, Inc. |
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| 7:10pm - 7:35pm |
Bus Transfer |
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| 7:30pm - 11:00pm |
Gala Dinner at Wasserwerk |
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| 8:30am - 9:15am |
Keynote 3 Location: MOA 10-12 "Challenges and Opportunities of Semiconductor Packaging in the Chiplet Era" Dr. Yasumitsu Orii Senior Managing Executive Officer in 3D Assembly Division, Rapidus Corporation |
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| 8:30am - 1:45pm |
Exhibition Location: Atrium |
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| 9:15am - 10:30am |
MIP4_Mechanical properties of Materials for Interconnects Location: MOA 10-12 Chair: Glenn Hamilton Ross, Aalto University Prediction of High Strain Rate Properties of Bi-doped SnAgCu Solders after Sustained High-temperature Operation 9:40am - 10:05am Quantification of Adhesion Strength and Mechanism of Adhesion Degradation Between Sputtered SUS304 and Mold Resin in Electromagnetic Wave Shield Packages 10:05am - 10:30am Effect of Minor Element Addition on Mechanical Properties and Microstructure of Sn-Bi Alloys |
AP7_Fan Out Packages Location: MOA 5 Chair: Erik Jung, Fraunhofer IZM INVITED TALK: Accelerating the AI Economy through Heterogeneous Integration 9:40am - 10:05am Development of an Adaptive Re-distribution Patterning Process for Fan-out Packages with Embedded High I/O Components 10:05am - 10:30am On the Design and Fabrication of SMT-compatible 3D-Freeform Antennas Based on Compression Molding and Direct Cu-Metallization |
AMT4_Hybrid Bonding, Direct Bonding, Heterogeneous Integration Location: MOA 4 Chair: Hoang-Vu Nguyen, University of South-Eastern Norway First Electrical Performance of Self-assembly Applied to Die-to-wafer Hybrid Bonding 9:40am - 10:05am BiCMOS BEOL Coupon Fabrication and Micro Transfer Printing for Heterogeneous Integration Applications 10:05am - 10:30am Impact of Dielectric Types & Surface Profile on Wafer-to-Wafer Hybrid Bonding |
Flex1_Reliability Assessment of Flexible Electronics Location: MOA 3 Chair: Jean Charles Souriau, CEA-Leti Development and Reliability Assessment of a Flexible Printed Capacitive Sensor for Precise Twisting Movement Detection 9:40am - 10:05am Reliability Assessment of Temperature Sensors Integrated on Elastic Substrate 10:05am - 10:30am Comparison of Electrical and Mechanical Properties of Stretchable Circuit Boards |
RF1_Millimeter-wave and Sub-THz Antenna-in-Package Integration for High Performance Systems Location: MOA 1+2 Chair: Matthias Wietstruck, IHP - Leibniz Institut für innovative Mikroelektronik Thin-Film Substrate-based mmWave Antennas for Automotive Radar Applications 9:40am - 10:05am Fabrication and Implementation of BiCMOS BEOL Silicon Interposer Technologies with Integrated Metal Reflectors for Sub-THz Leaky-wave Antennas 10:05am - 10:30am Broadband Antennas for High Performance 5G mmWave Modules |
| 10:30am - 11:00am |
Coffee Break & Exhibition Location: Atrium |
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| 10:30am - 11:45am |
Poster Session 3 Location: Atrium Chair: Karl-Friedrich Becker, Fraunhofer IZM An Overview of the Thick Film Copper Technology for Power Electronics Monitoring Cu via Structures and Surrounding Dielectric Stack After CMP Process Simulations of Thermocouple Measurements During Reactive Bonding Processes on LTCC Substrates Modelling the Influence of Stretched Molding Foil on the Overall Dimensions of Molded Packages. Mitigating Gas-induced Performance Degradation in High Reliability Electronic and Optoelectronic Systems Ag and SiO2 Mixed Powder Sintering System Investigation of Side Wall Loss for Development of 6 µm Microbumps for 3D/2.5D Integration Improving The Thinning Module Robustness Vis-a-vis the Bonding Misalignment & the TBM EBR LidroCUT - Laser Processing in Liquids for New Packaging Applications Alignment Between Subsequent 3D Molding Layers for Optimized Performance of 3D Integrated Patch Antennas for Advanced Sensing Applications Use of 3D Printing Techniques in the Development of Electronic Systems, Support Stage in the Digital Transformation of the Laboratories Evolved Finite Difference Model to Investigate Humidity-related Failure Modes for Microelectronic and Power Electronic Devices Study of the Water and Steam Resistance of Thick Film Materials for Sensor Applications up to 300 °C Tape Automated Bonding of an ALPIDE Chip with Flexible PCB Direct Flip Chip Bonding on Laser Induced Graphene Structures for Low-cost Flexible Sensor Devices Reliable Fabrication Methodology for Consistent Supercapacitor Performance |
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| 11:00am - 12:15pm |
MIP5_Microstructural Properties of Materials for Interconnects Location: MOA 10-12 Chair: Kay Essig, ASE Group Effect of Electromigration on Micro Tensile Test Mechanical Properties and Micro Structure of Pure Copper 11:25am - 11:50am Thermal-Mechanical Analysis of Electroplated Copper for IC Packaging 11:50am - 12:15pm Study of Intermetallic Compound Evolution of Pure Sn and SnAg Alloy Solder on Single and Multi-layer Under-bump Materials |
AP8_Fan Out Reliability Aspects Location: MOA 5 Chair: Grace O'Malley, INEMI Power Delivery for AI/HPC Microprocessors 11:25am - 11:50am Reliability and RF Performance Assessment of Heterogeneous Integrated FO-WLP Test Structure Packages for Mixed RF Digital Front-End Application 11:50am - 12:15pm No Warpage and Fast Cure: UV-molding for FOWLP/FOPLP |
AMT5_Advanced Materials and Processes Location: MOA 4 Chair: Attila Géczy, Budapest University of Technology and Economics Thin Substrate Bonding 11:25am - 11:50am System-in-package Building block Development for Future Space Equipment 11:50am - 12:15pm Single Die Process Using Shadow Masks for a 55µm Fine Pitch Array of 4µm-tall Indium Bumps Across an Entire Chip |
Flex2_Formation of a Conductive Interconnection for Flexible Electronics Location: MOA 3 Chair: Jukka Hast, VTT Technical Research Centre of Finland ltd. Additively Manufactured Flexible Electronics with Selectively Soldered Surface-mounted Devices Utilising StarJet Technology 11:25am - 11:50am Electroless Nickel/Immersion Gold and Immersion Tin as Final Finish Solutions for Flexible Substrates in EV Batteries 11:50am - 12:15pm Electrical Characterization of an ALPIDE Chip TAB Bonded with Flexible PCBs |
Rel3_Progress in Failure Analytical and Material Testing Methods Location: MOA 1+2 Chair: Matthias Petzold, Fraunhofer IMWS Full-field IR-Thermography for Bond-quality Inspection of Electroplated Aluminium Interconnects for Cryo-SiP Architectures 11:25am - 11:50am Using µ-RAMAN Spectroscopy to Inspect Sintered Interconnects 11:50am - 12:15pm Determination of Mechanical Properties for Copper in Plated Through Holes by Combination of Tensile Test and Nanoindentation |
| 12:15pm - 1:45pm |
Lunch |
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| 1:45pm - 3:00pm |
MIP6_New materials for Heterogeneous Integration Location: MOA 10-12 Chair: Nikhilendu Tiwary, Aalto University Development of Novel BT Laminate Materials for mmWave Antenna and Heterogeneous Integration 2:10pm - 2:35pm Parylene as a Novel Material for Adhesive Bonding, Flexible Electronics and Wafer Level Packaging 2:35pm - 3:00pm Manufacturing and Characterization of Thin-Film Tantalum Pentoxide Integrated Capacitors |
AP9_Power Electronics Packaging Location: MOA 5 Chair: Klaus Pressel, Infineon Additive Fan-out Panel-level Processing for Power MOSFET Devices 2:10pm - 2:35pm Advancing Packaging Solutions: Integrating Power Electronics Using LTCC Technology 2:35pm - 3:00pm Thermal Diffusivity Investigation of a Heat Pipe |
AMT6_Enhanced Process Control Location: MOA 4 Chair: Knut E. Aasmundtveit, University of South-Eastern Norway Invited Paper: A Novel Approach for Wafer level Solder Reflow and Cleaning of Semiconductor Wafer in Silicon Photonics, MEMS and Advanced Packaging 2:10pm - 2:35pm In-situ Measurement of HCOOH, CO2 and H2O Concentrations During Formic Acid Reflow Soldering 2:35pm - 3:00pm Enhanced Process Control for Dry Etching of Functional TiN Structures on 300 mm Wafer Level. |
RF2_Embedded System-in-Package and Interconnections Technologies Location: MOA 3 Chair: Maurizio Cirillo, Rheinmetall Italia SpA Integration of Microwave SMD Components into Organic Multilayer PCBs 2:10pm - 2:35pm Integration of III-V Components of 5G Transceiver in Embedding PCB-based Technology 2:35pm - 3:00pm Passive Intermodulation Estimation of a Novel Printed Circuit Board Interconnection Technology Based on Static I-V |
Rel4_New Approaches in Reliability Simulation and Modelling Location: MOA 1+2 Chair: Olaf Wittler, Fraunhofer IZM AI-Driven Digital Twin for Real-Time Health Monitoring of Wide Band Gap Semiconductors in Power Electronic Applications 2:10pm - 2:35pm Damage Parameter: Proposed Index to Quantify the Durability of Sintered Nano Silver and Multilayer Aluminum Foil Die Attach Materials 2:35pm - 3:00pm Energy-Based Approach on Calculating Stand-off Height of Different Solder Joints |
| 3:00pm - 3:10pm |
Room Change Location: Atrium |
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| 3:10pm - 3:55pm |
Keynote 4 Location: MOA 10-12 "CHIPS -NAPMP: Overview and Next Steps" George Orji Deputy Director of CHIPS NAPMP, USA |
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| 3:55pm - 4:25pm |
Closing |
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| 8:30am - 3:30pm |
IEEE EPS Board of Governors Meeting (not public) |