Conference Agenda

19th Electronics Packaging Technology Conference

Date: Friday, 08/Dec/2017
8:30am
-
9:00am
Invited-06: Wafer Bonding – An Enabling Technology for 3DIC, MEMS, BSI CIS, SOI, RF Filters, and More : Eric Pabo(EVG)
Location: Paradiso Room
Invited-07: VCSEL-based Optical Interconnects and Their Packaging Technologies : Dr. Hideyuki Nasu(Furukawa Electric Co)
Location: Cardinal Room
Invited-08: Temporary Bonding Materials for Fan-out Packaging Processes : Ram Trichur(Brewer Science)
Location: Swallow Room
Invited-09: On-Chip Embedded Cooling of Power and Logic Components : Dr. Avram Bar-Cohen(Raytheon Corporation)
Location: Lyrebird Room
Invited-10: Reliability Assurance: A Semiconductor Supplier’s Perspective : Dr. Stevan G. Hunter(ON Semiconductor)
Location: Falcon Room
9:00am
-
10:20am
D-01: ID 104
D-02: ID 170
D-03: ID 230
D-04: ID 171
D-05: ID 198
D-06: ID 266
D-07: ID 288
D-08: ID 292
D-09: ID 173
D-10: ID 243
D-11: ID 305
D-12: ID 298
D-13: ID 181
D-14: ID 192
D-15: ID 268
D-16: ID 281
D-17: ID 214
D-18: ID 189
D-19: ID 265
D-20: ID 279
S-16: Interconnection Technologies
Location: Paradiso Room
Chair: Chan Pin Chong
S-17: Emerging Technologies
Location: Cardinal Room
Chair: Yan Cheong Chan
S-18: Material and Processing
Location: Swallow Room
Chair: Rajoo Ranjan
S-19: Thermal Characterization & cooling solutions
Location: Lyrebird Room
Chair: GONG YUE TANG
S-20: Quality, Reliability & FA
Location: Falcon Room
10:20am
-
11:10am
Coffee/Tea Breaks #3: Exhibitor Pressentation
11:10am
-
12:30pm
E-01: ID 124
E-02: ID 275
E-03: ID 247
E-04: ID 186
E-05: ID 236
E-06: ID 153
E-07: ID 116
E-08: ID 195
E-09: ID 196
E-10: ID 252
E-11: ID 159
E-12: ID 222
E-13: ID 218
E-14: ID 211
E-15: ID 125
E-16: ID 254
E-17: ID 251
E-18: ID 103
E-19: ID 228
E-20: ID 278
S-21: Materials and Processing
Location: Paradiso Room
Chair: Kenzo Ohkita
S-22: Advanced Packaging
Location: Cardinal Room
Chair: Jean Charbonnier
S-23: TSV/Wafer Level Packaging
Location: Swallow Room
Chair: Boo Yang Jung
S-24: Electrical Simulations & Characterization
Location: Lyrebird Room
Chair: Eldon Staggs
S-25: Mechanical Modeling & Simulations
Location: Falcon Room
Chair: Yong Han
12:30pm
-
1:30pm
Lunch 02: Introduction of 20th Electronic Packaging Technology Conference
Location: Grand Ballroom
1:30pm
-
2:00pm
Invited-11: Advanced eWLB FOWLP: Enabling Integrated Packaging Solutions : Dr. Seung Wook Yoon(STATS ChipPAC)
Location: Paradiso Room
Invited-12: Highly accurate TSV, PWB and FO-PLP wiring fabication by plasma dry processes for interface : Dr. Yasuhiro Morikawa(ULVAC)
Location: Cardinal Room
Invited-13: 10 Golden Rules of Chip- Package- Board Interactions : Dr. E.Napetschnig(Infineon Technologies Austria)
Location: Swallow Room
Invited-14: Heterogeneous Integration Roadmap – Global Collaboration : William Chen(ASE, IEEE Electronic Packaging Society)
Location: Lyrebird Room
Invited-15: Interconnect Reliability Assurance Through Electrical Testing : Prof. Tan Cher Ming(Chang Gung University, Taiwan)
Location: Falcon Room
2:00pm
-
3:20pm
G-01: ID 151
G-02: ID 304
G-03: ID 120
G-04: ID 249
G-05: ID 257
G-06: ID 209
G-07: ID 177
G-08: ID 105
G-09: ID 244
G-10: ID 245
G-11: ID 179
G-12: ID 250
G-13: ID 217
G-14: ID 161
G-15: ID 270
G-16: ID 174
G-17: ID 221
G-18: ID 114
G-19: ID 253
G-20: ID 233
S-26: Advanced Packaging
Location: Paradiso Room
S-27: TSV/Wafer Level Packaging
Location: Cardinal Room
Chair: INDERJIT SINGH
S-28: Interconnection Technologies
Location: Swallow Room
Chair: Guilian Gao
S-29: Emerging Technologies
Location: Lyrebird Room
Chair: Jun Su Lee
S-30: Electrical Simulations & Characterization
Location: Falcon Room
Chair: Ranauld Perez
3:20pm
-
3:50pm
Coffee/Tea Break #04: Interactive session #2
3:50pm
-
4:20pm
Keynote speech 3: Design tools and modelling for power electronics packages – current status and future challenges : Prof. Bailey(University of Greenwich)
4:20pm
-
4:40pm
Closing Ceremony: Lucky Draw